This disclosure relates to data processing.
Data processing arrangements can make use of pipelined decoding and execution of instructions. The decoding process involves, as part of its functionality, allocating processor resources to the decoded instructions. The processor resources may be, for example, processor registers or register mappings and/or entries in buffers or the like such as re-order buffers, renaming lists or reservation stations.
Some arrangements make use of so-called cumulative status registers, for example relating to floating point operations.
Here, the term “cumulative” indicates that once a register has been “set”, it remains “set” until an explicit operation takes place to “unset” it. Therefore, if one of the registers is in a set condition, this indicates that the respective condition has occurred at some point since the last time the register was unset. In examples, a “set” register can be represented by a value 1 at the relevant bit position or data field, and an “unset” register can be represented by the value 0 at the relevant bit position or data field. However, other representations and/or pluralities can be used.
In the case of out of order execution, measures are used to provide for the setting of such cumulative status registers in response to instruction execution.